Size reduction of metal-oxide-semiconductor field-effect transistors (MOSFETs) has enabled continued improvement in speed, performance, density, and cost per unit function of integrated circuits. One way to further improve MOSFET performance is through selective application of stress to the transistor channel region. Stress distorts (i.e., strains) the semiconductor crystal lattice, and the distortion, in turn, affects the band alignment and charge transport properties of the semiconductor. By controlling the magnitude and distribution of stress in a finished device, carrier mobility (e.g., electron or hole mobility) can be increased and this improves device performance.
One approach of introducing stress in the transistor channel region includes growing an epitaxial layer of silicon germanium within recesses in the source/drain regions. In this approach, lattice mismatch between the epitaxial silicon germanium and the silicon substrate is used to create a uni-axial compressive stress within the channel region, which results in enhanced hole mobility. This occurs because the silicon germanium lattice constant is greater than the underlying substrate lattice constant.
High germanium concentration in epitaxial silicon germanium may be needed to effectively boost channel compressive strain in PMOS devices. Dopant atoms such as boron may be incorporated into the epitaxial silicon germanium to provide the required semiconductor doping to form source/drain regions of the P-type transistor, and to lower sheet resistance and thus improve contact resistance in the silicon germanium source drain regions. However, as technology nodes scale, it is increasingly difficult to precisely locate dopant atoms. Specifically, in conventional processing, dopant placement accuracy is limited to dimensions defined by lithography photomasks. Semiconductor areas are masked and dopant is either introduced through implantation or epitaxy. Either method is limited by the masking precision.
Accordingly, it is desirable to provide a method for fabricating an integrated circuit in which a layer of increased dopant concentration is formed without limitation of lithography photomasks. Further, it is desirable to provide a method for fabricating an integrated circuit in which formation of a layer of increased dopant concentration is controlled via different epitaxial growth rates on different crystalline planes. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.